The present disclosure generally relates to plasma mediated ashing processes that include formation of a protective layer before and/or during a plasma mediated ashing process.
Plasma mediated ashing, also referred to as stripping, generally refers to an integrated circuit manufacturing process by which residual organic material such as photoresist and post etch residues are stripped or removed from a substrate upon exposure to the plasma. The ashing process generally occurs after an etching or implant process has been performed in which a photoresist material is used as a mask for etching a pattern into the underlying substrate or for selectively implanting ions into the exposed areas of the substrate. The remaining photoresist and any post etch or post implant residues on the wafer after the etch process or implant process is complete must be removed prior to further processing for numerous reasons generally known to those skilled in the art. The ashing step can be followed by a wet chemical treatment to remove traces of the residue.
It is important to note that ashing processes significantly differ from etching processes. Although both processes may be plasma mediated, an etching process is markedly different in that the plasma chemistry is chosen to permanently transfer an image into the substrate by removing portions of the substrate surface through openings in a photoresist mask. The etching plasma generally includes high-energy ion bombardment at low temperatures and low pressures (of the order of millitorr) to remove portions of the substrate. Moreover, the portions of the substrate exposed to the ions are generally removed at a rate equal to or greater than the removal rate of the photoresist mask. In contrast, ashing processes generally refer to selectively removing the photoresist mask and any polymers or residues formed during etching. The ashing plasma chemistry is much less aggressive than etching chemistries and is generally chosen to remove the photoresist mask layer at a rate much greater than the removal rate of the underlying substrate. Moreover, most ashing processes heat the substrate to temperatures greater than 80° C. to increase the plasma reactivity, and are performed at relatively higher pressures (on the order of a torr). Thus, etching and ashing processes are directed to removal of significantly different materials and as such, require completely different plasma chemistries and processes. Successful ashing processes are not used to permanently transfer an image into the substrate. Rather, successful ashing processes are defined by the photoresist, polymer and residue removal rates without affecting or removing underlying layers, e.g., the substrate, low k dielectric materials, and the like.
As devices transition into the 32 nanometer (nm) regimes and beyond, there is growing concern with plasma mediated damage caused by plasma mediated stripping processes. One such area of concern is with the removal of photoresist exposed to high doses during ion implantation in the transistor formation. Typically, sensitive substrate materials such as silicon (implanted, often with very shallow dopants), SiGe, high-k dielectrics, metal gates, etc. are exposed during the photoresist removable process and substrate damage can occur. The substrate damage may be in the form of substrate erosion (e.g., etching, sputtering, physical removal of a portion of the substrate) or by substrate oxidation. The substrate oxidation is undesirable as it will change the electrical, chemical, and physical properties of the substrate layer. For example, in a source and drain implant application, a patterned photoresist layer is formed over the silicon substrate at the source and drain regions prior to carrying out a high dose implant. During the high dose implant, the photoresist is subjected to high energy ions that induce cross-linking reactions to harden an upper shell of the photoresist, commonly referred to as the crust. The physical and chemical properties of the crust vary depending on the implant conditions. Because of this, more aggressive chemistries are needed to remove the resist. At the same time, however, extremely shallow junction depths are calling for very high selectivity. Silicon loss or silicon oxidation from the source/drain regions must be avoided during the high-dose ion implantation strip. For example excessive silicon loss can deleteriously alter the current saturation at a given applied voltage as well as result in parasitic leakage due to decreased junction depth detrimentally altering electrical functioning of the device. The International Technology Roadmap for Semiconductors (ITRS) projects target silicon loss for the 45 nm generation to be 0.4 angstroms per cleaning step and 0.3 angstroms for the 32 nm generation.
Current plasma mediated stripping processes are typically oxygen based followed by a wet clean step. However, oxygen based plasma processes can result in significant amounts of substrate surface oxidation, typically on the order of about 10 angstroms or more. Because silicon loss is generally known to be governed by silicon surface oxidation for plasma resist stripping processes, the use of these oxygen based plasma strip processes by themselves is considered by many to be unacceptable for 45 and 32 nm technology node where almost “zero” substrate loss is required and new materials are introduced such as embedded SiGe source/drain, high-k gate dielectrics, metal gates and NiSi contact which are extremely sensitive to surface oxidation.
Accordingly, there remains a need for improved photoresist resist stripping processes, especially as it relates to the removal of photoresist exposed to high dose implantation.